Evaluation Of ‘Cache’ Memory Performance Variation On Size Variation

Authors

Amit Kumar Research Scholar/Amrita Vishwa Vidyapeetham, Coimbatore, Tamil Nadu, India Author
R. S. Kumar Department of Information Technology/Amrita Vishwa Vidyapeetham, Coimbatore, Tamil Nadu, India Author

Spatial Locality, Temporal Locality, CPU, Intel ‘cache’, Data Buffer.

To mitigate the discrepancy between processor and main memory speeds, ‘cache’s are added to a system. A ‘cache’ is a

quick, tiny memory that sits between the main memory and the processor. The ‘‘cache’’s access time is matched by the

processor’s cycle time. Therefore, the ‘‘cache’ memory’ of system should be able to reply to a memory request in about

10ns if the processor is operating at a 100MHz speed. ‘‘cache’ memory’ is actually constructed on the ‘processor chip’ and

divided into separate instruction and data ‘cache’s in today’s high-performance single-chip CPUs. These ‘cache’s typically

have a size of 8 KB, so that the CPU chip has 16 KB of ‘cache’ overall. An off-chip ‘cache’, commonly known as the second-

level ‘cache’ or L2 ‘cache’, is also a common feature of system designs.